The present invention relates to an information processing system, such as a personal computer (PC), and in particular to an information processing system with a power saving function that reduces the operating frequency of a processor (a so-called CPU: Central Processing Unit) that assumes responsibility for data processing in the system, or halts the operation of the processor, for the purpose of reducing power consumption. More specifically, the present invention pertains to an information processing system that satisfies both requests for power saving and for security of the system, and that can reduce the operating frequency of the CPU or can halt the operation of the CPU, even during a period in which communication with another independent apparatus is taking place.
As progress in the current technique continues, various types of personal computers (hereafter referred to as "PCs" or "systems"), such as desktop and notebook computers, are being manufactured and widely sold. The notebook PCs that are being manufactured are compact and light, since for their design, portability and outdoor use are taken into consideration.
One of the features of notebook PCs is that they are "battery operable" and can be driven by an incorporated battery. Such a system can be used at sites where there are no commercially available power sources. A battery that is incorporated in a notebook PC is commonly formed as a "battery pack", which is a package that is comprised of a plurality of rechargeable battery cells, such as Ni-Cd, NiMH, or Li-Ion (also called a "secondary cell"). Although such a battery pack is reusable by recharged, the battery duration is sufficient to supply power for only two to three hours of system operation time. Therefore, various ideas for power saving have been implemented to extend the time between charge periods for a battery. The introduction of the power saving function can constitute another feature of the notebook PC.
At present, from an ecological point of view, the demand for power saving is increasing, even for desktop PCs to which power can be supplied almost endlessly by commercially available power sources. And in June 1993, the U.S. Environmental Protection Agency (EPA) advocated the self-imposed regulations that are collectively called the "Energy Star Computer Program", and required that power consumed in the standby state be lower than a predetermined value (driving power is to be 30 W or less, or 30% or less than it is when the CPU is active). Computer makers have developed and manufactured products that conform to the suggested regulation. For example, desktop PCs that have a power saving function are already sold by IBM Japan, Ltd. (e.g., the PS/55E (for which "Green PC" is a common name), PC 750, and the Aptiva series ("Aptiva" is a trademark of IBM Corp.)).
Power saving with a PC can be accomplished by, for example, reducing power consumption by the individual electric circuits during the operation. Power savings can also be provided by reducing or halting, as needed, the power supply to the individual electric circuits (or devices) in the system in accordance with the reduction of the operational state (activity). The latter power saving function may especially be called a "Power Management" function.
The power management modes of a PC are an "LCD backlight-OFF" mode and an "HDD-OFF" mode, which halts of the power supply to devices, such as an LCD (Liquid Crystal Display) and its backlight, or a rotary motor of an HDD (hard disk drive), that account for the greatest share of the total power consumption by a whole system. The other example power management modes are a "CPU slow clock/stop clock" mode, in which the operating frequency of a CPU (Central Processing Unit) is reduced or the operation of the CPU is halted, and a "Suspend" mode, in which the power supply to all the electric circuits, except for a main memory, is halted after data that are required for resuming the task are saved in the main memory.
As is well known, CPU chips are the units that constitute the nuclei for the computations that are performed by computer systems. Recently, as production techniques for manufacturing semiconductor devices have improved, as is demonstrated by the reduction in the wiring width, the operational frequencies of CPUs have increased even more. For example, there have appeared CPU chips, such as the "Pentium", which is sold by Intel Corp., and the "PowerPC" (a trademark of IBM Corp.), that can be driven at operational frequencies that exceed 100 MHz. The performance of a CPU and its operating frequency are very closely related. As the operational speed of a CPU rises, the speed at which it performs calculations increases accordingly. A fast CPU demonstrates its excellent capabilities especially when running large application programs and when performing graphics procedures.
But as nothing is perfect, the high processing speed of CPUs brings with it several problems. One of the problems concerns the increased power consumption by the CPUs and the consequent heat generation. As the strength of a current that passes across a transistor gate (i.e., a resistor) per unit time increases, the power consumption and the heat generation also increase. Theoretically, the power consumption by a CPU is proportional to the operating frequency. Currently, the ratio of the power consumption by a CPU to the total power consumption by the system can not be ignored.
The power management functions of the CPU, such as the "CPU slow clock/stop clock", are provided to overcome the above described condition. The "slow clock" and the "stop clock" are modes in which, when the system determines that a CPU is in the standby state or is in the idle state because a predetermined time has elapsed since a last key/mouse input, power consumption is reduced by lowering the operating frequency of the CPU (i.e., by reducing the performance of the CPU), or by halting its operation. It should be noted that the performance of the CPU is lowered only up to the point at which neither turn-around time (i.e., the time that is required from the reception of a request until the generation of an affirmative response) nor through-put (the quantity of jobs per unit time) is deteriorated. The "slow clock" and the "stop clock" functions of the CPU will be described below.
The slow clock function of the CPU can be achieved by changing the frequency of a clock signal input by an external oscillator. This function can also be achieved by changing a CPU chip's internal operating frequency while maintaining a constant input clock frequency to the CPU chip. A high speed processing CPU ordinarily receives a relatively low clock signal (for example, 66 MHz) and internally increases the speed of an operation clock (to, for example, double the speed, 133 MHz) by using an incorporated PLL (Phase Lock Loop) circuit. It is difficult for this type of CPU to drastically change an input clock frequency provided to the CPU chip because of the characteristic of a PLL circuit (e.g., the inherent vibration count of an oscillator or a delay time (several msec) required until the phase locking is performed). Therefore, another design method is employed for a CPU chip that incorporates not only a PLL circuit but also a slow clock function (power management function) that can internally change an operating clock. According to this method, the incorporated PLL circuit usually increases an input clock speed while the internal slow clock function autonomously lowers the performance of the CPU in the chip.
FIG. 8 is a schematic diagram illustrating the internal arrangement of a CPU that incorporates a power management function. In FIG. 8, a CPU chip 11 comprises a functional unit 11a that actually performs computation, etc.; a PLL circuit 11b that transmits, to the functional unit 11a, an operating clock signal for synchronous driving; and a performance controller 11c that controls the performance of the functional unit 11a. The CPU chip 11 communicates with its peripheral devices (not shown) via a processor bus 12.
The function of a PLL circuit whereby the frequency of an input clock signal is multiplied is well known. The PLL circuit 11b doubles the speed (66 MHz, for example) of a relatively slow clock signal to obtain an operating frequency (133 MHz, for example), and transmits the doubled clock signal to the functional unit 11a.
The functional unit 11a can be divided into a computation unit (a double shaded portion in FIG. 8) and an internal cache/control unit. The computation unit is a section whose performance can, to a degree, be reduced in accordance with the activity of the system (it should be noted that the performance of the computation unit can be lowered only to the degree that the turn around time and the through-put are not deteriorated). The internal cache/control unit is a section that must respond to an external event, such as a cache snoop, an interrupt request (INTR/NMI/SMI), or a hold request (HOLD) of the bus 12, that occurs unperiodically and in a time critical manner, and as a result, its performance can not be easily reduced.
The performance controller 11c controls the performance of the functional unit 11a in response to a control signal STPCLK# received from an external device. More specifically, while the STPCLK# is active (i.e., low), the controller 11c halts the supply of the operating frequency to the computation unit (the double shaded portion in FIG. 8) in the functional unit 11a. That is, the CPU chip 11 is so designed that its performance can be reduced locally. As a modification method, the STPCLK# that is to be inputted to the performance controller 11c is intermittently changed to active (i.e., goes low) to reduce the frequency of the operating clock transmitted from the PLL circuit 11b. For example, if the STPCLK# is set active (i.e., goes low) according to a predetermined cycle and the frequency of the operating clock is reduced by one of n times, the performance and power consumption of the computation unit is reduced to about (n-1)/n. The function that intermittently affects the STPCLK# input operation is generally called "clock throttling" or "frequency emulation".
In the slow clock mode, the input clock from the oscillator 40 and the operation of the PLL circuit 11b are not changed from those in the normal high speed operational mode. Therefore, recovery from the slow clock mode to the normal mode can be performed relatively rapidly. This matter should be well noted to understand the subject of the present invention, which will be described later.
SL enhanced 486s, DX2s and DX4s, and Pentiums, which are chips that have succeeded the "80486" CPU chip from Intel Corp., have the power saving function that is shown in FIG. 8. These chips include the STPCLK# as one of control signals on the processor bus 12.
The "stop clock" function completely prevents the input clocks from the oscillator 40, and halts the entire functional unit 11a. The complete stopping of the operating clock can be accomplished by virtue of a fully static arrangement of the CPU chip 11 in which a storing and saving function is not required. In the "stop clock" mode, the power consumption by the CPU is, at most, several hundreds of mW.
Since the PLL circuit 11b is also halted in the stop clock mode, a delay time of approximately 1 msec is required to stabilize the operation of the PLL circuit 11b (lock the phase) to recover to the normal high speed mode. This matter should be well noted to understand the subject of the present invention, which will be described later.
The power management operation, such as the slow clock/stop clock of the CPU, is commonly accomplished by cooperative functions involving hardware, which is provided outside of the CPU chip, that monitors the state of the system, and software executed by the CPU.
A specific software example for achieving the power management is the "APM" (Advanced Power management) that is jointly proposed by Intel Corp. and Microsoft Corp. The APM takes effect in the OS (Operating System) environment that is compatible with to the APM. The APM compatible OS environment is a system that is constituted by 1) hardware for which power saving is required, 2) a BIOS (also called an "APM BIOS") that actually performs the hardware operations required for power management, 3) an OS that can call the APM BIOS as the operational state (activity) of the system becomes lowered, and 4) an application that is compatible with the APM. For 1), the hardware is, for example, a CPU chip that has a slow clock/stop clock function. For 3), the APM compatible OS is, for example, PC DOS J6.1/V or any succeeding version, OS/2 J2.1 or any succeeding version ("OS/2" is a trademark of IBM Corp.), or Windows J3.1 or any succeeding version. The APM compatible OS generally includes an "APM" driver that calls an APM BIOS. For 4), the APM compatible application is an application program that registers itself in the APM driver via an API (Application Program Interface) to receive an inquiry for the start of the power management operation and to provide an affirmative response to the inquiry.
When software, such as the APM, that is resident in the OS is employed, the power management operation of the CPU involves the following procedures:
(1) When there is no effective task to be executed in a queue of a scheduler ("scheduler" is one of the modules in the OS), i.e., the system must wait for a next effective task to occur, it is ascertained that the CPU is in the idle state. PA1 (2) In response to the detection of the idle state of the CPU, the APM driver calls the APM BIOS. The APM driver may exchange, with the APM application, the inquiry and the affirmative response for the start of power management. PA1 (3) The APM BIOS, upon the call, performs hardware operation to shift the system to the power management state. For example, the APM BIOS performs intermittent throttling of the STPCLK# in order to shift the system to the slow clock state, or halts the input of a clock to the CPU chip 11 in order to shift the system to the stop clock state.
Since the OS can employ its own scheduler and can detect information in advance to the effect that "the system will enter the operation standby state", the power management operation can be efficiently carried out by a method using the APM.
The OS, however, can control only its own system. The OS can have no knowledge of the operational state, for example, of another independent apparatus (another PC) with which the system is physically connected and is communicating with via a communication port (a serial port or a parallel port). That is, the OS can manage a task for transmitting data from its own system, but can not detect an event wherein another independent apparatus has begun data transmission. Since data transfer is performed at a relatively high speed, the CPU must be fully active in order not to miss the data transfer. For example, if the CPU is in the slow clock state when another apparatus begins data transmission, some delay is caused in a data reception process performed by the CPU and data will be lost. And if the CPU is in the stop clock state when another apparatus begins data transmission, even though the CPU is to be recovered to the normal mode in response to the data reception, it takes some time before the operation of the CPU is stabilized, as is previously described, and the data transmitted to the CPU during that time will be lost. In short, if only the internal state of its own system is taken into consideration and the power management operation is begun by preference merely because the queue in the OS is empty, data exchanged will be lost, and as a result, the security of the system will be substantially degraded.
Regarding the security of the system as more important than the power saving effect, most of the PCs that are currently being sold on the market are so designed that the lowering of the performance of the CPU is thoroughly inhibited during a period when the system is exchanging data with another independent apparatus (for example, another PC). Or the PCs are so designed that the performance of the CPU is not lowered during the execution of the communication application (the communication application does not provide an affirmative response even upon the receipt of a power management request from the APM driver, and thus, the APM BIOS is not called). Therefore, though the CPU chip has a higher performance for power management (e.g., see FIG. 8), the system can utilize this function only when the CPU falls completely into the standby state (i.e., for a relatively long time). The period during which the CPU is fully in the standby state is very limited and is, at most, 1) when a predetermined time has elapsed since a last key input (e.g., Japanese Examined Patent Publication No. 06-95303, the fourth paragraph), or 2) when DMA transfer is performed because at this time the CPU relinquishes the control of its own local bus (e.g., Japanese Unexamined Patent Publication No. 06-266462). If the CPU enters the slow clock state or the stop clock state only during such a limited period, the obtained power management effect is not satisfactory. If possible, more opportunities during which the performance of the CPU can be lowered are desired. Even while data are exchanged with another independent apparatus via a communication port, for example, it is desired that the performance of the CPU be lowered to enhance the power management effect.